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8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 1 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer b lock d iagram p in a ssignment f eatures ? eleven differential 3.3v lvpecl outputs ? differential reference clock input pair ? ref_clk, nref_clk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum output frequency: 700mhz ? maximum reference clock input frequency: 200mhz ? vco range: 250mhz - 700mhz ? accepts any single-ended input signal with a resistor bias on nclk input ? external feedback for zero delay capabilitiy ? output skew: 70ps (maximum) ? cycle-to-cycle jitter: 65ps (maximum) ? full 3.3v operating supply ? 0c to 70c ambient operating temperature ? available in both standard and lead-free rohs compliant packages 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 mr v cco q8 nq8 q9 nq9 v ee q10/fb_out nq10/nfb_out v cco fb_in nfb_in v cco nq3 q3 nq2 q2 v ee nq1 q1 nq0 q0 v cco nc div_sel2 div_sel1 div_sel0 v cca v ee ref_clk nref_clk fb_sel1 fb_sel0 v cc v ee nc pll_sel v cco q4 nq4 q5 nq5 v ee q6 nq6 q7 nq7 v cco 48-lead lqfp 7mm x 7mm x 1.4mm package body y package top view g eneral d escription the ics8731-01 is a low voltage, low skew, 1-to-11 differential-to-3.3v lvpecl clock mul- tiplier/zero delay buffer and a member of the hiperclocks? family of high performance clock solutions from ics. with output frequen- cies up to 700mhz the ics8731-01 is targeted at high perfor- mance clock applications. along with a fully integrated pll the ics8731-01 contains frequency configurable, differential outputs and external feedback inputs for multiplying clock frequencies and regenerating clocks with ?zero delay?. fre- quency multiplication is achieved by utilizing the separate feedback and clock output dividers. the value of the multi- plier is determined by the ratio of the feedback divider, m, to the output divider, n. for multiplier values greater than 1, m must be greater than n. for multiplier values less than 1, m must be less than n. the zero delay mode is achieved with m and n at equal values. the divide values of the clock and feedback outputs are controlled by the div_sel0:2 and fb_sel0:1 inputs, respectively. the ics8731-01 accepts any differential signal and translates it to differential 3.3v lvpecl output levels. ics8731-01 hiperclocks? ic s pll 0 1 2 4 6 8 1 2 4 6 8 q0:q9 nq0:nq9 q10/fb_out nq10/nfb_out 100 000 001 010 011 00 01 10 11 div_sel0 div_sel1 div_sel2 ref_clk nref_clk fb_in nfb_in pll_sel mr fb_sel1 fb_sel0
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 2 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 1r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a s t u p t u o d e t r e v n i e h t d n a w o l o g o t , x q , s t u p t u o e u r t e h t g n i s u a c t e s e r s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t x q n . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a , 0 1 , 2 , 6 3 , 6 2 8 4 , 8 3 v o c c r e w o p. s n i p y l p p u s t u p t u o , 4 , 3 6 , 5 , 8 q n , 8 q 9 q n , 9 q t u p t u o. s r i a p t u p t u o l a i t n e r e f f i d , 0 2 , 4 1 , 7 3 4 , 1 3 v e e r e w o p. s n i p y l p p u s e v i t a g e n , 8 9 , t u o _ b f / 0 1 q t u o _ b f n / 0 1 q n t u p t u o. s t u p t u o k c o l c l a i t n e r e f f i d 2 1 , 1 1n i _ b f n , n i _ b ft u p n in w o d l l u p h t i w s k c o l c g n i t a r e n e g r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . " y a l e d o r e z " 5 1v c c r e w o p. n i p y l p p u s e r o c 6 10 l e s _ b ft u p n in w o d l l u p . ) 3 e l b a t e e s ( s t u p t u o b f / 0 1 q r o f r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 11 l e s _ b ft u p n in w o d l l u p . ) 3 e l b a t e e s ( s t u p t u o b f / 0 1 q r o f r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8 1k l c _ f e r nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 9 1k l c _ f e rt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 1 2v a c c r e w o p. n i p y l p p u s g o l a n a 2 2, 0 l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 21 l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 22 l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5 2 , 3 1c nd e s u n u. t c e n n o c o n 8 2 , 7 2 0 3 , 9 2 , 0 q n , 0 q 1 q n , 1 q t u p t u o. s r i a p t u p t u o l a i t n e r e f f i d , 3 3 , 2 3 5 3 , 4 3 , 2 q n , 2 q 3 q n , 3 q t u p t u o. s r i a p t u p t u o l a i t n e r e f f i d 7 3l e s _ l l pt u p n ip u l l u p e h t o t t u p n i e h t s a k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s s t c e l e s , h g i h n e h w . k c o l c e c n e r e f e r s t c e l e s , w o l n e h w . s r e d i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . l l p , 0 4 , 9 3 2 4 , 1 4 , 4 q n , 4 q 5 q n , 5 q t u p t u o. s r i a p t u p t u o l a i t n e r e f f i d , 5 4 , 4 4 7 4 , 6 4 , 6 q n , 6 q 7 q n , 7 q t u p t u o. s r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 3 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer t able 3a. c ontrol i nput f unction t able for q0:q9 o utputs s t u p n is t u p t u o r ml e s _ l l p2 l e s _ v i d1 l e s _ v i d0 l e s _ v i d9 q n : 0 q n , 9 q : 0 q 1 xxxx w o l 01100 1 / o c v f 0 1000 2 / o c v f 01001 4 / o c v f 01010 6 / o c v f 01011 8 / o c v f 00100 1 / k l c _ f e r f 0 0000 2 / k l c _ f e r f 00001 4 / k l c _ f e r f 00010 6 / k l c _ f e r f 00011 8 / k l c _ f e r f t able 3b. c ontrol i nput f unction t able for q10/fb s t u p n is t u p t u o r ml e s _ l l p1 l e s _ b f0 l e s _ b fb f / 0 1 q n , b f / 0 1 q 1xxx w o l 0100 2 / o c v f 0101 4 / o c v f 0110 6 / o c v f 0111 8 / o c v f 0000 2 / k l c _ f e r f 0001 4 / k l c _ f e r f 0010 6 / k l c _ f e r f 0011 8 / k l c _ f e r f t able 3c. q x o utput f requency w /fb_in = q10/fb s t u p n io c v f n i _ b f1 l e s _ b f0 l e s _ b f b f / 0 1 q e d o m r e d i v i d t u p t u o ) z h m ( k l c _ f e r ) 1 e t o n ( m u m i n i mm u m i x a m b f / 0 1 q00 2 5 2 1) 2 e t o n ( 0 0 22 x k l c _ f e r f b f / 0 1 q01 4 5 . 2 65 7 14 x k l c _ f e r f b f / 0 1 q10 6 7 6 . 1 47 6 . 6 1 16 x k l c _ f e r f b f / 0 1 q11 8 5 2 . 1 35 . 7 88 x k l c _ f e r f . z h m 0 0 7 o t z h m 0 5 2 s i e g n a r y c n e u q e r f o c v : 1 e t o n . z h m 0 0 2 s i t p e c c a n a c r o t c e f e d e s a h p e h t t a h t y c n e u q e r f t u p n i m u m i x a m e h t : 2 e t o n
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 4 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 9 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m t able 4b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i , 0 l e s _ v i d , l e s _ l l p , 2 l e s _ v i d , 1 l e s _ v i d r m , 1 l e s _ b f , 0 l e s _ b f 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i , 0 l e s _ v i d , l e s _ l l p , 2 l e s _ v i d , 1 l e s _ v i d r m , 1 l e s _ b f , 0 l e s _ b f 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , 1 l e s _ v i d , 0 l e s _ v i d , r m , 2 l e s _ v i d 1 l e s _ b f , 0 l e s _ b f v c c v = n i v 5 6 4 . 3 =0 5 1a l e s _ l l pv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i , 1 l e s _ v i d , 0 l e s _ v i d , r m , 2 l e s _ v i d 1 l e s _ b f , 0 l e s _ b f v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a l e s _ l l p v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 5 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer t able 4d. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 - t able 4c. d ifferential dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i n i _ b f , k l c _ f e rv c c v = n i v 5 6 4 . 3 =0 5 1a n i _ b f n , k l c _ f e r nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i n i _ b f , k l c _ f e rv c c v , v 5 6 4 . 3 = n i v 0 =5 -a n i _ b f n , k l c _ f e r nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v n i _ b f n , n i _ b f d n a k l c _ f e r n , k l c _ f e r r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n v s i c c . v 3 . 0 + s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o nv h i . t able 6. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? , v 0 = l e s _ l l p z h m 0 5 40 . 45 . 5s n t ) ? (2 e t o n ; t e s f f o e s a h p c i t a t s , v 3 . 3 = l e s _ l l p , 0 0 0 = ] 0 : 2 [ l e s _ v i d 0 0 = ] 0 : 1 [ l e s _ b f 0 50 5 1s p t ) o ( k s4 , 3 e t o n ; w e k s t u p t u o 0 7s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y c 5 6s p t l e m i t k c o l l l p 1s m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 7s p c d oe l c y c y t u d t u p t u o? z h m 0 0 35 45 5% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n l a n g i s t u p n i k c a b d e e f e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 5. pll i nput r eference c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f f e r y c n e u q e r f e c n e r e f e r t u p n i 0 0 2z h m
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 6 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer p arameter m easurement i nformation o utput s kew d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v c ycle - to -c ycle j itter -1.3v 0.165v t sk(o) nqx qx nqy qy v cmr cross points v pp v cc v ee ref_clk nref_clk o utput r ise /f all t ime p ropagation d elay o utput d uty c ycle /p ulse w idth /p eriod s tatic p hase o ffset clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = q0:q9, q10/fb_out nq0:nq9, nq10/fb_out ? ? ? ? t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 q0:q9, q10/fb_out nq0:nq9, nq10/fb_out (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset ? ? t (?) v oh v ol v oh v ol nref_clk nfb_in ref_clk fb_in v cc , v cca , v cco v ee t pd ref_clk nref_clk q0:q9, q10/fb_out nq0:nq9, nq10/fb_out
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 7 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics8731-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput r2 1k v cc clk_in + - r1 1k c1 0.1uf v_ref w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609.
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 8 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer f igure 3c. h i p er c lock s ref_clk/nref_clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s ref_clk/nref_clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s ref_clk/nref_clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the ref_clk /nref_clk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input require- ments. figures 3a to 3d show interface examples for the hiperclocks ref_clk/nref_clk input driven by the most common driver types. the input interfaces suggested here f igure 3a. h i p er c lock s ref_clk/nref_clk i nput d riven by ics h i p er c lock s lvhstl d river are examples only. please consult with the vendor of the driver component to confirm the driver termination require- ments. for example in figure 3a, the input termination ap- plies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termina- tion recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 9 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 10 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer zo = 50 to logic input pins u1 8731-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mr vcco q8 nq8 q9 nq9 vee q10/qfb nq10/nqfb vcco fb_in nfb_in nc vee vcc fb_sel0 fb_sel1 nref_clk ref_clk vee vcca div_sel0 div_sel1 div_sel2 vcco nq3 q3 nq2 q2 vee nq1 q1 nq0 q0 vcco nc vcco nq7 q7 nq6 q6 vee nq5 q5 nq4 q4 vcco pll_sel r5 50 r10 50 (u1-26) vcc + - c4 0.1uf c16 10uf c5 0.1uf c1 0.1uf r9 50 bypass capacitors located near the power pins zo = 50 zo = 50 c3 0.1uf c2 0.1uf (u1-10) vcc=3.3v vcca c11 0.1uf (u1-48) vcc r2 50 r4 50 set logic input to '1' vcco=3.3v vcco r1 50 rd1 spare vcco 3.3v zo = 50 r8 50 zo = 50 c6 0.1uf vcc logic input pin examples ru1 1k rd2 1k (u1-38) r13 10 r3 50 + - r6 50 (u1-36) r7 50 ru2 spare c11 0.1uf r11 50 vcc lvpecl (u1-2) set logic input to '0' zo = 50 to logic input pins r12 50 s chematic e xample figure 5 shows an application schematic example of the ics8731-01. this schematic provides examples of input and output handling. the input can accept various types of differen- tial signal. this example shows the ics8731-01 input driven by a 3.3v lvpecl driver. additional examples for the input driven by other types of drivers are shown in the application section of f igure 5. a pplication s chematic e xample this data sheet. the ics8731-01 outputs are lvpecl driver. in this example, we assume the traces are long transmission line and the receiver is high input impedance without built-in matched load. an example of 3.3v lvpecl termination is shown in this schematic. additional termination approaches are shown in the lvpecl termination application note.
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 11 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8731-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8731-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 195ma = 675.67mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 11 * 30mw = 330mw total power _max (3.465v, with all outputs switching) = 675.67mw + 330mw = 1005.67mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 1.006w * 42.1c/w = 112.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 7. t hermal r esistance ja for 48- pin lqfp, f orced c onvection 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 12 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc - v oh_max )) /r l ] * (v cc - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc - v ol_max )) /r l ] * (v cc - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 13 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer r eliability i nformation t ransistor c ount the transistor count for ics8731-01 is: 2883 t able 8. ja vs . a ir f low t able for 48 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 14 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer p ackage o utline - y s uffix for 48 l ead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c b b m u m i n i ml a n i m o nm u m i x a m n 8 4 a 0 6 . 1 1 a 5 0 . 05 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 5 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 5 . 5 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 7 c c c 8 0 . 0 t able 9. p ackage d imensions reference document: jedec publication 95, ms-026
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 15 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - y c 1 3 7 8 s c i1 0 - y c 1 3 7 8 s c ip f q l d a e l 8 4y a r tc 0 7 o t c 0 t 1 0 - y c 1 3 7 8 s c i1 0 - y c 1 3 7 8 s c ip f q l d a e l 8 4l e e r & e p a t 0 0 0 1c 0 7 o t c 0 f l 1 0 - y c 1 3 7 8 s c il 1 0 y c 1 3 7 8 s c ip f q l " e e r f - d a e l " d a e l 8 4y a r tc 0 7 o t c 0 t f l 1 0 - y c 1 3 7 8 s c il 1 0 y c 1 3 7 8 s c ip f q l " e e r f - d a e l " d a e l 8 4l e e r & e p a t 0 0 0 1c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
8731cy-01 www.icst.com/products/hiperclocks.html rev. a june 6, 2006 16 integrated circuit systems, inc. ics8731-01 l ow s kew , 1- to -11 d ifferential - to -3.3v lvpecl c lock m ultiplier / z ero d elay b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 0 1 t 1 5 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f . e t o n d n a g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 6 0 / 6 / 6

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